1. Field of the Invention
The present invention relates to PECL/LVPECL input buffers, and more particularly, to a PECL/LVPECL input buffer that employs positive feedback to provide input hysteresis, symmetric headroom, and high noise immunity.
2. Description of the Related Art
Emitter coupled logic (ECL) is a family of bipolar logic building blocks that employ low impedance, non-saturating output drivers. For this reason, ECL is capable of reaching very high operating speeds, such as those required for high speed serial communication. ECL can be regarded as having two supply voltages: a positive upper supply voltage VCC that is equal to ground (0V), and a negative lower supply voltage VEE that is 5.2V below ground, or −5.2V.
The ECL logic 1voltage VOH and the ECL logic 0voltage VOL are both referenced to the positive upper supply voltage VCC (which is at ground level, or 0V). Thus, the nominal VOH voltage for ECL is equal to (VCC−0.9V), or −0.9V, and the nominal VOL voltage for ECL is equal to (VCC−1.7V), or −1.7V.
One common variation of ECL is known as ‘pseudo ECL’ or PECL. PECL is similar to ECL in that it employs the same high speed, low impedance, non-saturating output drivers that are capable of reaching very high operating speeds. PECL differs from ECL, however, in that PECL employs a positive upper supply voltage VCC that is equal to +5V, and a lower supply voltage VEE that is equal to ground (0V). Therefore, an extremely important advantage of PECL over ECL is that PECL can provide a CMOS compatible interface.
As with ECL, the PECL logic 1voltage VOH and the PECL logic 0 voltage VOL are both referenced to the positive upper supply voltage VCC (which is equal to +5V). Thus, the nominal VOH voltage for PECL is equal to (VCC−0.9V), or +4.1V, and the nominal VOL voltage for PECL is equal to (VCC−1.7V), or +3.3V. Since both of the PECL logic levels are referenced to the VCC voltage, both logic levels will vary when the VCC voltage varies. This logic level variation with the VCC voltage is extremely important, because it profoundly influences the design of CMOS compatible PECL input buffers.
There is a variation of PECL known as low voltage PECL (LVPECL). LVPECL is similar to PECL, in that LVPECL employs the same high speed, low impedance, non-saturating output drivers that are capable of reaching very high operating speeds. LVPECL differs from PECL, however, in that LVPECL employs a +3.3V upper supply voltage VCC, in lieu of the +5V VCC voltage employed by PECL. Therefore, the main advantage of LVPECL over PECL is that LVPECL can interface to CMOS chips that utilize a ‘low’ VCC voltage of 3.3V.
As with PECL, the LVPECL logic 1voltage VOH and the LVPECL logic 0voltage VOL are both referenced to the positive upper supply voltage VCC (which is equal to +3.3V). Therefore, the nominal VOH voltage for LVPECL is equal to (VCC−0.9V), or +2.4V, and the nominal VOL voltage for LVPECL is equal to (VCC−1.7V), or +1.6V.
As with PECL, both of the LVPECL logic levels are referenced to VCC, so both logic levels will vary when the VCC voltage varies. Therefore, as with PECL, this logic level variation with the VCC voltage is extremely important, because it profoundly influences the design of CMOS compatible LVPECL input buffers.
Although PECL and LVPECL input buffers employ different VCC voltages, the logic level difference for both technologies is exactly the same: (VCC−0.9V)-(VCC−1.7V), or 800 mv. Furthermore, because this logic level difference is independent of the VCC supply voltage, it is possible to construct non-standard LVPECL circuits that operate from VCC supply voltages that are less than +3.3V.
For example, LVPECL circuits can be constructed using a nominal VCC supply voltage of only +2.5V. Of course, the main reason for employing a +2.5V non-standard VCC supply voltage is that this voltage allows non-standard LVPECL circuits to directly interface to CMOS chips that utilize a +2.5V VCC supply. However, since this +2.5V VCC supply voltage is non-standard, the systems designer must ensure that the LVPECL drivers and LVPECL receivers both operate from the same non-standard +2.5V VCC supply voltage. Nevertheless, in order to be deemed LVPECL compatible, CMOS chips must employ a +3.3V supply voltage.
As with standard LVPECL, the non-standard LVPECL logic 1voltage VOH and the non-standard LVPECL logic 0voltage VOL are both referenced to the positive upper supply voltage VCC (which is equal to +2.5V). Thus, the nominal VOH voltage for non-standard LVPECL is equal to (VCC−0.9V), or +1.6V, and the nominal VOL voltage for non-standard LVPECL is equal to (VCC−1.7V), or +0.8V.
FIG. 1 shows a timing diagram 100 that illustrates an example of the voltage levels for a prior art PECL signal PS. As shown in FIG. 1, the power supply voltage VCC can vary by ±10% from its nominal value of +5V. As a result, the minimum, typical, and maximum values of VOH and VOL, for the PECL signal PS, will also vary by ±10%.
FIG. 2 shows a timing diagram 200 that illustrates an example of the voltages of a prior art LVPECL signal LS. As shown in FIG. 2, the power supply voltage VCC can vary by ±10% from its nominal value of +3.3V. As a result, the minimum, typical, and maximum values of VOH and VOL, for the LVPECL signal LS, will also vary by ±10%.
FIG. 3 shows a timing diagram 300 that illustrates an example of the voltages of a prior art non-standard (+2.5V) LVPECL signal NS. As shown in FIG. 3, the power supply voltage VCC can vary by ±10% from its nominal value of +2.5V. As a result, the minimum, typical, and maximum values of VOH and VOL, for the LVPECL voltage signal NS, will also vary by ±10%.